module top;
wire o,a1;

system_clk #100 clk2(a1);
nanf201 c1 (o,a1);
endmodule

module nanf201(o,a1);
input a1;
output o;
not(o,a1);
specify
specparam
tpd_0_1=1.13:3.09:7.75,
tpd_1_0=0.93:2.5:7.34;
(a1=>o)=(tpd_0_1,tpd_1_0);
endspecify
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(49*period/50)clk=~clk;
#(period-49*period/50)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule