Verilog 期末考

module top;
system_clk #50 clk1(a);
system_clk #100 clk2(b);
system_clk #200 clk3(c);
system_clk #400 clk4(d);
pig p1 (f,a,b,c,d);
endmodule

module pig (f,a,b,c,d);
input a,b,c,d;
output f;
wire a1,b1,c1,d1,w,x,y,z;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w,d1,c1,b,a1);
and(x,d,b1,a1);
and(y,d,b,a);
and(z,d1,c,a);
or(f,w,x,y,z);
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

module top;
reg A,B;
wire D;
nand_f n1(C,A,B);
not_f n1(D,C);

initial begin
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b1;
#2 A=1'b0;
#10$finish;
end
endmodule


module nand_f(C,A,B);
input A,B;
output C;
nand(C,A,B);
specify
specparam
tpd_0_1=3.0:3.0:3.0,
tpd_1_0=3.0:3.0:3.0;
(A=>C)=(tpd_0_1,tpd_1_0);
(B=>C)=(tpd_0_1,tpd_1_0);
endspecify
endmodule
module not_f(D,C);
input C;
output D;
not(D,C);
specify
specparam
tpd_0_1=2.0:2.0:2.0,
tpd_1_0=2.0:2.0:2.0;
(C=>D)=(tpd_0_1,tpd_1_0);
endspecify
endmodule